1. Field of the Invention
This invention relates to the identification of the proper feedback tap configuration which defines a binary pseudonoise (PN) code sequence generator capable of recreating an observed code sequence. The proper feedback tap configuration identification is based on the rapid testing and elimination of hypothesis tap configurations. This invention provides a method and apparatus to rapidly test a large number of code hypothesis, even though the observed code sequence is corrupted by noise.
2. Description of Prior Art
In the paper "Acquisition of Pseudonoise Signals by Recursion Aided Sequential Estimation," by R. B. Ward and K. P. Yiu, IEEE Transactions on Communications, Vol. COM-25, No. 1, August 1977, the authors present a technique for the acquisition of a known direct sequence spread spectrum (DSSS) signal based on sequential estimation. The PN code generator uses an arrangement similar to that used for the discrepancy detection logic circuit presented by James L. Massey in his paper "Shift-Register Synthesis and BCH Decoding," IEEE Transactions on Information Theory, Vol. IT-15, No. 1, January 1969, with the addition of an integrator to average the value of the discrepancy bit over time. In the prior art of James C. Fletcher (U.S. Pat. No. 3,953,674), he extended the technique of Ward and Yiu to include non-NRZ format signals. Here the integrator was implemented using an 11-bit counter. In the present invention, the discrepancy detection logic circuit of Massey has been extended to include a discrepancy integrator, and further extended to the simultaneous parallel processing of previously stored time samples. Thus, the time integration is performed instantaneously, allowing the hypothesis testing of a large set of code sequences in a timely manner.